View PCF8548U2_821626.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
PCF8548 65 x 102 pixels matrix LCD driver
Product specification Supersedes data of 1999 Mar 22 File under Integrated Circuits, IC12 1999 Aug 16
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
CONTENTS 1 2 3 3.1 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 8.1 8.2 8.3 8.4 8.5 8.6 9 10 10.1 10.2 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 FEATURES APPLICATIONS GENERAL DESCRIPTION Packages ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS R0 to R64: row driver outputs C0 to C101: column driver outputs VSS1 and VSS2: negative power supply rails VDD1 to VDD3: positive power supply rails VLCDIN: LCD power supply VLCDOUT: LCD power supply VLCDSENSE: voltage multiplier regulation input (VLCD) T1 to T12: test pads SDAIN and SDAOUT: I2C-bus data lines SCL: I2C-bus clock signal SA0: slave address OSC: oscillator RES: reset BLOCK DIAGRAM FUNCTIONS Oscillator I2C-bus interface Display control logic Display Data RAM (DDRAM) Timing generator LCD row and column drivers INITIALIZATION ADDRESSING Display data RAM structure RAM access I2C-BUS INTERFACE Characteristics of the I2C-bus Bit transfer START and STOP conditions System configuration Acknowledge I2C-bus protocol 12 12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.3 12.3.1 12.4 12.4.1 12.4.2 12.5 12.6 12.7 12.7.1 12.8 12.9 12.10 13 14 15 16 17 18 19 20 21 22 23 24 25 26 INSTRUCTIONS External reset (RES) Function set Power-Down (PD) V H MX MY Display control D and E Display configuration TRS BRS Set Y address of RAM Set X address of RAM Set HV generator stages S[1:0] Temperature control Bias system Set VOP value LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS RESET
PCF8548
APPLICATION INFORMATION CHIP INFORMATION PAD INFORMATION DEVICE PROTECTION DIAGRAM TRAY INFORMATION DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS BARE DIE DISCLAIMER
1999 Aug 16
2
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
1 FEATURES
PCF8548
* Single-chip LCD controller/driver * 65 row and 102 column outputs * Display data RAM 65 x 102 bits * On-chip: - Configurable 5 (4, 3 and 2) x voltage multiplier generating VLCD (external VLCD also possible) - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible). * 400 kbits/s fast I2C-bus interface * CMOS compatible inputs * Mux rate: 1 : 65 * Logic supply voltage range VDD1 to VSS: - 1.9 to 5.5 V. * High voltage generator supply voltage range VDD2 to VSS and VDD3 to VSS: - 2.4 to 4.5 V with LCD voltage internally generated (voltage generator enabled). * Display supply voltage range VLCD to VSS: - 4.5 to 9.0 V * Low power consumption, suitable for battery operated systems * Temperature compensation of VLCD * Slim chip layout, suitable for Chip-On-Glass (COG) applications * Programmable bottom row pads mirroring and top row pads mirroring, for compatibility with both Tape Carrier Package (TCP) and COG applications. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8548U/2 PCF8548U/9 Tray Bumped wafer chip with bumps in tray quarter wafer DESCRIPTION VERSION - - 2 APPLICATIONS * Telecom equipment * Portable instruments * Point of sale terminals. 3 GENERAL DESCRIPTION
The PCF8548 is a low power CMOS LCD controller driver, designed to drive a graphic display of 65 rows and 102 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8548 interfaces to most microcontrollers via an I2C-bus interface. 3.1 Packages
The PCF8548 is available as chip with bumps in tray; tape carrier package is available on request.
1999 Aug 16
3
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
5 BLOCK DIAGRAM
PCF8548
handbook, full pagewidth
VDD1
VDD2
VDD3
C0 to C101 102
R0 to R64 65 ROW DRIVERS
VSS1 VSS2 RES
PCF8548
COLUMN DRIVERS
VLCDIN
BIAS VOLTAGE GENERATOR
DATA LATCHES
SHIFT REGISTER
OSCILLATOR VLCDSENSE VLCDOUT HIGH VOLTAGE GENERATOR 4 STAGES DISPLAY DATA RAM 65 x 102 BITS TIMING GENERATOR
OSC
I2C-BUS INTERFACE
DISPLAY CONTROL LOGIC
SDAOUT SDAIN SCL
SA0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12
MGS393
Fig.1 Block diagram.
6
PINNING SYMBOL PAD 1 2 3 and 4 5 and 6 7 8 9 to 11 12 and 13 14 15 to 20 21 to 26 28 to 33 34 DESCRIPTION external reset input (active LOW) I2C-bus data output I2C-bus data input I2C-bus clock input test 2 output least significant bit of slave address test inputs test input/output test input negative power supply 1 negative power supply 2 voltage multiplier output voltage multiplier regulation input (VLCD) SYMBOL VLCDIN R32 to R19 R0 to R18 C0 to C101 R50 to R33 R51 to R64 T12 to T9 OSC T8 VDD1 VDD3 VDD2 PAD 35 to 40 41 to 54 57 to 75 76 to 177 178 to 195 198 to 211 212 to 215 216 217 218 to 223 224 to 226 227 to 233 DESCRIPTION LCD supply voltage LCD row driver outputs LCD row driver outputs LCD column driver outputs LCD row driver outputs LCD row driver outputs test outputs oscillator test input supply voltage 1 supply voltage 3 supply voltage 2
RES SDAOUT SDAIN SCL T2 SA0 T7 to T5 T4 and T3 T1 VSS1 VSS2 VLCDOUT VLCDSENSE
27, 55, 56, dummy pads 196 and 197
1999 Aug 16
4
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
7 7.1 PIN FUNCTIONS R0 to R64: row driver outputs 7.8 T1 to T12: test pads
PCF8548
These pads output the row signals. 7.2 C0 to C101: column driver outputs
T1 and T3 to T7 must be connected to VSS1. T8 must be connected to VDD1. T2 and T9 to T12 must be left open-circuit; not accessible to user. 7.9 SDAIN and SDAOUT: I2C-bus data lines
These pads output the column signals. 7.3 VSS1 and VSS2: negative power supply rails
VSS2 is related to VDD2 and VDD3 and VSS1 is related to VDD1. 7.4 VDD1 to VDD3: positive power supply rails
VDD2 and VDD3 are the supply voltages for the internal voltage generator. Both have to be at the same voltage and must be connected together outside of the chip. If the internal voltage generator is not used, they should both be connected to power or to the VDD1 pad. VDD1 is used as the power supply for the rest of the chip. This voltage can be a different voltage than VDD2 and VDD3. 7.5 VLCDIN: LCD power supply
Serial data and acknowledge lines for the I2C-bus. By connecting SDAIN to SDAOUT, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF8548 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. 7.10 SCL: I2C-bus clock signal
Internally generated positive power supply for the liquid crystal display. An external LCD supply voltage can be supplied using the VLCDIN pad. In this case, VLCDOUT has to be connected to ground, and the internal voltage generator has to be programmed to zero. If the PCF8548 is in power-down mode, the external LCD supply voltage must be switched off. 7.6 VLCDOUT: LCD power supply
I2C-bus serial clock signal input. 7.11 SA0: slave address
Two different slave addresses can be selected using the SA0 pad. This allows two PCF8548 LCD drivers to be connected to the same I2C-bus. 7.12 OSC: oscillator
Positive power supply for the liquid crystal display. If the internal voltage generator is used, the two supply rails VLCDIN and VLCDOUT must be connected together and an external capacitor must be connected (see Fig.19). 7.7 VLCDSENSE: voltage multiplier regulation input (VLCD)
When the on-chip oscillator is used this input must be connected to VDD1. An external clock signal, if used, is connected to this input. 7.13 RES: reset
This signal is used to reset the device. The signal is active LOW.
VLCDSENSE is the input voltage for the internal voltage multiplier regulation. If the internal voltage generator is used then VLCDSENSE must be connected to VLCDOUT. If an external supply voltage is used then VLCDSENSE must be connected to ground.
1999 Aug 16
5
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
8 8.1 BLOCK DIAGRAM FUNCTIONS Oscillator 8.5 Timing generator
PCF8548
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD1. An external clock signal (if used), is connected to this input. 8.2 I2C-bus interface
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the I2C-bus. 8.6 LCD row and column drivers
The I2C-bus interface receives and executes the commands sent via the I2C-bus. It also receives RAM data and sends it to the RAM. 8.3 Display control logic
The PCF8548 contains 65 row and 102 column drivers, which connect the appropriate LCD bias voltages to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected. 9 INITIALIZATION
The display control logic generates the control signals to read from the RAM via the 102 bits parallel port. It also generates the control signals for the row and column drivers. 8.4 Display Data RAM (DDRAM)
Immediately following Power-on, all internal registers and the RAM content are undefined. A reset pulse must first be applied. Reset is accomplished by applying an external RES pulse (active LOW). When reset occurs within the specified time all internal registers are initialized, however the RAM is still undefined. The state after reset is described in Section 12.1. The RES input must be 0.3 VDD when VDD reaches VDD(min) (or higher) within a maximum time tVHRL after VDD goes HIGH (see Fig.17).
The PCF8548 contains a 65 x 102 bit static RAM which stores the display data. The RAM is divided into 8 banks of 102 bytes and 1 bank of 102 bits [(8 x 8 + 1) x 102 bits]. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and column output number.
1999 Aug 16
6
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
frame n
VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS
frame n + 1 Vstate1(t) Vstate2 (t)
ROW 0 R0 (t)
ROW 1 R1 (t)
COL 0 C0 (t)
COL 1 C1 (t)
VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD
Vstate1(t)
Vstate2 (t)
0 1 2 3 4 5 6 7 8...
... 64 0 1 2 3 4 5 6 7 8...
... 64
MGS671
Vstate1(t) = C1(t) - R0(t). Vstate2(t) = C1(t) - R1(t).
Fig.2 Typical LCD driver waveforms.
1999 Aug 16
7
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
DDRAM
bank 0 top of LCD
bank 1
bank 2
LCD
bank 3
bank 7
bank 8
MGS395
Fig.3 DDRAM to display mapping.
1999 Aug 16
8
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
10 ADDRESSING
PCF8548
The Display Data RAM (DDRAM) of the PCF8548 is accessed as indicated in Figs 3, 6, 7, 8 and 9. The DDRAM has a matrix of 65 x 102 bits. The RAM cells are addressed by the X and Y address pointers. The address ranges are X0 to X101 (1100101b) and Y0 to Y8 (1000b). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1) the Y address increments after each byte (see Fig.5). After the last Y address (Y = 8), Y wraps around to 0 and X increments to address the next column. In the horizontal addressing mode (V = 0) the X address increments after each byte (see Fig.4). After the last X address (X = 101), X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101 and Y = 8) the address pointers wrap around to address X = 0 and Y = 0. 10.1 Display data RAM structure
handbook, full pagewidth
0 102 204 306 408 510 612 714 816 0
1 103 205 307 409 511 613 715 817
2 104 206 308 410 512 614 716 818 X address 917 101
0
Y address
8
MGS396
Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
1999 Aug 16
9
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 0
9 10
0
Y address
917 X address 101
8
MGS397
Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
The DO bit defines the bit order (MSB on top or MSB on bottom) for writing to the RAM (see Figs 6 and 7).
handbook, full pagewidth MSB
LSB
MSB
MGS398
LSB
Fig.6 RAM byte organization, if DO = 0.
1999 Aug 16
10
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth LSB
MSB
LSB
MGS399
MSB
Fig.7 RAM byte organization, if DO = 1.
The MX bit allows a horizontal mirroring; when MX = 1, the X address space is mirrored. The address X = 0 is then located at the right side (column 101) of the display (see Fig.9). When MX = 0 the mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.8).
handbook, full pagewidth
0
8
0
X address Y address
101
MGS400
Fig.8 RAM format addressing (MX = 0).
1999 Aug 16
11
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
0
8
101
X address Y address
0
MBL044
Fig.9 RAM format addressing (MX = 1).
10.2
RAM access
If the D/C bit is logic 1 the RAM can be written to. The data is written to the RAM during the acknowledge cycle.
1999 Aug 16
12
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
11 I2C-BUS INTERFACE 11.1 Characteristics of the I2C-bus
PCF8548
* Slave: the device addressed by a master * Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices. 11.1.4 ACKNOWLEDGE
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.1.1 BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.10. 11.1.2 START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.11. 11.1.3 SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.12. * Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Fig.13.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.10 Bit transfer.
1999 Aug 16
13
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.11 Definition of START and STOP conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.12 System configuration.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.13 Acknowledgement on the I2C-bus.
1999 Aug 16
14
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
11.2 I2C-bus protocol
PCF8548
The control and data bytes are also acknowledged by all addressed slaves on the bus. After the last control byte, depending on the D/C bit setting, either a series of display data bytes or command data bytes may follow. If the D/C bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended PCF8548 device. If the D/C bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed slave. At the end of the transmission the I2C-bus master issues a STOP condition (P). If the R/W bit is set to logic 1 the chip will output data immediately after the slave address if the D/C bit, which was sent during the last write access, is set to logic 0. If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
The PCF8548 supports command, data write and status read access. Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8548. The least significant bit of the slave address is set by connecting the input SA0 to either logic 0 (VSS1) or logic 1 (VDD1). The I2C-bus protocol is illustrated in Fig.14. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and D/C, plus a data byte (see Fig.14 and Table 1). The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the D/C bit defines whether the data byte is interpreted as a command or as RAM data.
handbook, Write mode full pagewidth
acknowledgement from PCF8548 S S 0 1 1 1 1 0 A 0 A 1 DC 0 slave address
acknowledgement from PCF8548
acknowledgement from PCF8548
acknowledgement from PCF8548
acknowledgement from PCF8548
control byte
A
data byte
A 0 DC
control byte
A
data byte n 0 bytes MSB . . . . . . . . . . . LSB
AP
Co
2n 0 bytes command word
Co
1 byte
S R/ 011110AW 0 Read mode acknowledgement from PCF8548 S S011110A1A 0 slave address acknowledgement from master PCF8548 slave address
status bytes
AP
Co DC 0 0 0 0 0 0 A control byte
MGS401
Fig.14 I2C-bus protocol.
1999 Aug 16
15
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
12 INSTRUCTIONS The instruction format is divided into two modes: 1. If D/C is set LOW, commands can be sent to the chip. 2. If D/C is set HIGH, the DDRAM will be accessed. Every instruction can be sent in any order to the PCF8548. Table 1 Instruction set COMMAND BYTE INSTRUCTION H = 0 or 1 NOP Reserved Function set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 MX 0 0 MY 0 0 PD 0 0 V 0 1 H no operation do not use D/C R/W B7 B6 B5 B4 B3 B2 B1 B0
PCF8548
DESCRIPTION
Power-down control; entry mode; extended instruction set control (H) read status byte writes data to RAM
Read status byte Write data H=0 Reserved Set VLCD range Display control Set HV-gen stages Set Y address of RAM Set X address of RAM H=1 Reserved Temperature control Display configuration Bias system Reserved Set VOP
0 1
1 0
PD D7 0 0 0 0 0 1
TRS BRS D6 0 0 0 0 1 X6 D5 0 0 0 0 0 X5
D D4 0 0 0 1 0 X4
E D3 0 0 1 0 Y3 X3
MX D2 0 1 D 0 Y2 X2
MY D1 1 0 0 S1 Y1 X1
DO D0 X
0 0 0 0 0 0
0 0 0 0 0 0
do not use
PRS VLCD programming range select E S0 Y0 X0 sets display configuration # of HV-gen voltage multiplication sets Y address of RAM: 0Y8 sets X address of RAM: 0 X 101 do not use
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1
0 0 0 0 X
0 0 0 1 X
0 0 1 0 X
0 1 DO BS2 X
1 TC1
X
TC0 set temperature coefficient (TCx)
TRS BRS top/bottom row mode set data order BS1 X BS0 set bias system (BSx) X do not use (reserved for test)
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 write VOP to register
1999 Aug 16
16
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Table 2 Explanations of symbols in Table 1 BIT PD V H MX MY TRS BRS DO PRS D and E 00 10 01 11 TC[1:0] 00 01 10 11 S[1:0] 00 01 10 11 BS[2:0] Vop[6:0] 12.1 chip is active horizontal addressing use basic instruction set normal X addressing display is not vertically mirrored top rows are not mirrored bottom rows are not mirrored MSB is on top VLCD programming range LOW display blank normal mode all display segments on inverse video mode VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 2 x voltage multiplier 3 x voltage multiplier 4 x voltage multiplier 5 x voltage multiplier bias system VLCD programming 0 1 chip is in Power-down mode vertical addressing use extended instruction set X address is mirrored display is vertically mirrored top rows are mirrored bottom rows are mirrored LSB is on top VLCD programming range HIGH 1 0 0 0 0 0 0 0 0 D=0 E=0
PCF8548
RESET STATE
TC[1:0] = 00
S[1:0] = 00
BS[2:0] = 000 Vop[6:0] = 0000000
External reset (RES)
After power-on a reset pulse must be applied immediately to the chip, as it is in an undefined state. A reset of the chip can be achieved using the external reset pad. After the reset the LCD driver is set to the following states: * Power-down mode (PD = 1) * All LCD outputs at VSS (display off) * Horizontal addressing (V = 0) * Normal instruction set (H = 0) * Normal display (MX = MY = TRS = BRS = 0) * Display blank (E = D = 0) * Address counter X[6:0] = 0 and Y[3:0] = 0 * Temperature coefficient (TC[1:0] = 0) * Bias system (BS[2:0] = 0) * VLCD is equal to 0, the HV generator is switched off (Vop[6:0] = 0 and PRS = 0) * After power-on (RAM data is undefined), the reset signal does not change the content of the RAM.
1999 Aug 16
17
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
12.2 12.2.1 Function set POWER-DOWN (PD) 12.2.5 MY
PCF8548
When MY = 1, the display is mirrored vertically. A change of this bit has an immediate effect on the display. 12.3 12.3.1 Display control D AND E
* All LCD outputs at VSS (display off) * Bias generator and VLCD generator off * Oscillator off (external clock possible) * VLCD can be disconnected * RAM contents not cleared (RAM data can be written) * VLCD output is discharged to VSS. 12.2.2 V
The bits D and E select the display mode (see Table 2). 12.4 12.4.1 Display configuration TRS
When V = 0, the horizontal addressing is selected. The data is written to the RAM as shown in Fig.4. When V = 1, the vertical addressing is selected. The data is written to the RAM as shown in Fig.5. 12.2.3 H
When H = 0 the commands `display control', `set HV-gen stages', `set Y address' and `set X address' can be performed. When H = 1 the other commands can be executed. The commands `write data' and `function set' can be executed in both cases. 12.2.4 MX
Bit TRS enables the top row pad blocks to be mirrored. This is used to enable flexibility in the wiring of the row lines from the PCF8548 to the LCD cell (e.g. COG or TCP wiring). When TRS = 0 rows 19 to 32 and rows 51 to 64 are organized as illustrated in Fig.22. When TRS = 1 rows 19 to 32 and rows 51 to 64 are mirrored and organized as illustrated in Fig.23. 12.4.2 BRS
When MX = 0, the display RAM is written from left to right (X = 0 is on the left side of the display, X = 100 is on the right side of the display). When MX = 1 the display RAM is written from right to left (X = 0 is on the right side of the display, X = 100 is on the left side of the display). Thus, if a horizontally mirroring of the display is desired the RAM must first be rewritten. Table 3 Y3 0 0 0 0 0 0 0 0 1 Note 1. In bank 8 only the MSB is accessed. 1999 Aug 16 18 X and Y address ranges Y2 0 0 0 0 1 1 1 1 0 Y1 0 0 1 1 0 0 1 1 0 Y0 0 1 0 1 0 1 0 1 0
Bit BRS enables the bottom row pad blocks to be mirrored. This is used to enable flexibility in the wiring of the row lines from the PCF8548 to the LCD cell (e.g. COG or TCP wiring). When BRS = 0 rows 0 to 18 and rows 33 to 50 are organized as illustrated in Fig.22. When BRS = 1 rows 0 to 18 and rows 33 to 50 are mirrored and organized as illustrated in Fig.23. 12.5 Set Y address of RAM
Y[3 : 0] defines the Y address vector address of the RAM.
CONTENT bank 0 (display RAM) bank 1 (display RAM) bank 2 (display RAM) bank 3 (display RAM) bank 4 (display RAM) bank 5 (display RAM) bank 6 (display RAM) bank 7 (display RAM) bank 8 (display RAM); note 1
ALLOWED X RANGE 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
12.6 Set X address of RAM
PCF8548
There are 4 different temperature coefficients available in the PCF8548 (see Fig.15). The coefficients are selected by the two bits TC[1:0]. Table 6 shows the typical values of the different temperature coefficients. The coefficients are proportional to the programmed VLCD. 12.9 Bias system
The X address points to the columns. The range of X is 0 to 101 (65H). 12.7 12.7.1 Set HV generator stages S[1:0]
The PCF8548 incorporates a software configurable voltage multiplier. After reset the voltage multiplier is set to 2 x VDD2. Other voltage multiplier factors are set via the command `set HV-gen stages' (see Tables 1 and 2). 12.8 Temperature control
The Bias voltage levels are set in the ratio 1 of R - R - nR - R - R giving a ------------ bias system. n+4 The resulting bias levels are shown in Table 5. Different multiplex rates require different factors n (see Table 4); this is programmed by BS[2 : 0]. For Mux 1 : 65 the optimum bias value n is given by: n= m-3 = 65 - 3 = 5.06 = 5 resulting in 19bias.
Due to the temperature dependency of the liquid crystals viscosity, the LCD controlling voltage VLCD must be increased with lower temperature to maintain optimum contrast.
handbook, halfpage
MGS402
VLCD
Tcut
T
Fig.15 Temperature coefficients.
1999 Aug 16
19
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Table 4 Programming the required bias system BS[1] 0 0 1 1 0 0 1 1 LCD bias voltage BIAS VOLTAGES VLCD (n + 3)/(n + 4) (n + 2)/(n + 4) 2/(n + 4) 1/(n + 4) VSS
8 7 2 1 9 9 9
PCF8548
BS[2] 0 0 0 0 1 1 1 1 Table 5
BS[0] 0 1 0 1 0 1 0 1
n 7 6 5 4 3 2 1 0
RECOMMENDED MUX RATE 1 : 100 1 : 81 1 : 64 1 : 49 1 : 36 1 : 24 1 : 16 1:9
SYMBOL V1 V2 V3 V4 V5 V6
BIAS VOLTAGES FOR 19 BIAS VLCD
9 x VLCD
x VLCD x VLCD x VLCD VSS
The parameters are explained in Fig.16 and Table 6. The maximum voltage that can be generated is dependent on the VDD2 voltage and the display load current. Two overlapping VLCD ranges are selectable via the command `HV-gen control'. For the LOW (PRS = 0) range a = a1 and for the HIGH (PRS = 1) range a = a2 with steps equal to b in both ranges. It should be noted that the charge pump is turned off if VOP[6;0] and bit PRS are all set to zero. For Mux 1 : 65 the optimum operation voltage of the liquid can be calculated as follows: 1 + 65 V LCD = -------------------------------------- x V th = 6.85 x V th 1 1 - ---------- 2x 65 where Vth is the threshold voltage of the liquid crystal material used.
12.10 Set VOP value The voltage at reference temperature can be calculated as: [VLCD (T = Tcut)] V LCD
( Tcut )
= ( a + V OP x b )
(1)
The operating voltage VLCD can be set by software. The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at reference temperature (Tcut). V LCD = ( a + V OP x b ) x [ 1 + ( T - T cut ) x TC ] (2) Table 6 Typical values for parameters for the HV-generator programming SYMBOL a1 a2 b Tcut BITS VALUE 2.94 (PRS = 0) 6.75 (PRS = 1) 0.03 27 V V V C UNIT
1999 Aug 16
20
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
VLCD
b charge pump off a2 a1+b
a1
0H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH 00H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH LOW (PRS = 0) HIGH (PRS = 1)
MGS658
VOP[6:0] (programmed); 00H to 7FH, programme range LOW and HIGH.
Fig.16 VOP programming of PCF8548.
As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9.0 V) the customer must ensure while setting the VOP register and selecting the temperature coefficient, under all conditions and including all tolerances VLCD remains below 9.0 V.
1999 Aug 16
21
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
13 LIMITING VALUES Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134); parameters are valid over operating temperature range unless otherwise specified; all voltages referenced to VSS = 0 V. Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. SYMBOL VDD1 VDD2,VDD3 VLCD ISS Vi(n) II IO Ppack P/out supply voltage supply voltage for internal voltage generator supply voltage for the LCD supply current all input voltages DC input current DC output current power dissipation per package power dissipation per output PARAMETER MIN. -0.5 -0.5 -0.5 -50 -0.5 -10 -10 - - MAX. +6.5 +4.5 +9.0 +50 VDD + 0.5 +10 +10 300 30 V V V mA V mA mA mW mW UNIT
14 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices"). 15 DC CHARACTERISTICS VDD1 = 1.9 to 5.5 V; VDD2 and VDD3 = 2.4 to 4.5 V; VSS1 and VSS2 = 0 V; VLCD = 4.5 to 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL VDD1 VDD2,VDD3 PARAMETER supply voltage Tamb = -25 to +85 C supply voltage for internal voltage generator LCD input supply voltage LCD output supply voltage supply current LCD voltage internally generated (voltage generator enabled) LCD voltage externally supplied (voltage generator disabled) LCD voltage internally generated (voltage generator enabled); note 1 VDD1 = 2.8 V; VLCD = 7.6 V; fsclk = 0; Tamb = 25 C; notes 2 and 3 with external VLCD CONDITIONS MIN. 1.9 1.8 2.4 - - - TYP. MAX. 5.5 5.5 4.5 V V V UNIT
VLCDIN
4.5
-
9.0
V
VLCDOUT
4.5
-
9.0
V
IDD1
-
20
-
A
IDD2,IDD3
supply current for internal voltage generator
-
0.5 180
- -
A A
with internal VLCD generation; - VDD1 = 2.8 V; VLCD = 7.6 V; fsclk = 0; Tamb = 25 C; no display load; 4 x charge pump; notes 2 and 3 22
1999 Aug 16
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
SYMBOL IDD(tot)
PARAMETER total supply current
CONDITIONS with internal VLCD generation; - VDD1 = 2.8 V; VLCD = 7.6 V; fsclk = 0; Tamb = 25 C; no display load; 4 x charge pump; notes 2 and 3 (Power-down mode) with internal or external VLCD generation; note 4 -
MIN. 200
TYP.
MAX. 350
UNIT A
1.5
10
A
ILCDIN
supply current from external VLCD
VDD1 = 2.8 V; VLCD = 7.6 V; fsclk = 0; Tamb = 25 C; no display load; notes 2, 3 and 5
-
30
-
A
Logic VIL VIH IL Rrow LOW-level input voltage HIGH-level input voltage leakage current Vi = VDD1 or VSS1 VDD1 to VDD3 = 5.0 V; VLCD = 7.6 V; IL = 10 A; outputs tested one at a time VLCD = 7.6 V VSS1 0.7VDD1 -1 - - - - 12 0.3VDD1 VDD1 +1 V V A k
Column and row outputs row output resistance R0 to R64 column output resistance C0 to C101 column bias tolerance C0 to C101 row bias tolerance R0 to R64 20
Rcol Vbias(col) Vbias(row)
- -100 -100
12 0 0
20 +100 +100
k mV mV
LCD supply voltage generator VLCD VLCD tolerance internally generated VDD1 = 2.8 V; VLCD = 7.6 V; fsclk = 0; Tamb = 25 C; no display load; notes 2, 3 6 and 7 00 01 10 11 Notes 1. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. 2. Internal clock. 3. When fsclk = 0 there is no I2C-bus clock. 4. Power-down mode. During power-down all static currents are switched off. 5. If external VLCD, the display load current is not transmitted to IDD. 6. Tolerance depends on the temperature; (typically zero at Tamb = 27 C), maximum tolerance values are measured at the temperature range limit. 7. For TC0 to TC3. 1999 Aug 16 23 -300 0 +300 mV
TC
temperature coefficient
- - - -
-0.0 x 10-3 -0.76 x -1.05 x 10-3 10-3
- - -
1/C 1/C 1/C 1/C
-2.10 x 10-3 -
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
16 AC CHARACTERISTICS VDD1 = 1.9 to 5.5 V; VDD2 and VDD3 = 2.4 to 4.5 V; VSS1 and VSS2 = 0 V; VLCD = 4.5 to 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fOSC fclk(ext) fframe tVHRL tW(RES) PARAMETER oscillator frequency external clock frequency frame frequency VDD1 to RES LOW RES LOW pulse width fOSC or fclk(ext) = 38 kHz; note 1 see Fig.17 and note 2 see Fig.17 and note 3 CONDITIONS VDD1 = 2.8 V; Tamb = -20 to +70 C 20 20 - 0 100 MIN. TYP. 38 38 73 - - - - - - - - - - - - - - - - MAX. 70 100 - 1 - UNIT kHz kHz Hz s ns
I2C-bus timing characteristics; see note 4 fSCLK tSCLL tSCLH tSU;DAT tHD;DAT tr tf tf(SDA)(ro) Cb tSU;STA tHD;STA tSU;STO tSW tBUF Notes 1. f clk ( ext f frame = -----------------) 520 SCL clock frequency SCL clock LOW period SCL clock HIGH period data set-up time data hold time SCL and SDA rise time SCL and SDA fall time SDA fall time for read out capacitive load represented by each bus line set-up time for a repeated START condition START condition hold time set-up time for STOP condition tolerable spike width on bus bus free time between a STOP and START condition note 6 note 5 note 5 VDD1 = <3.6 V 0 1.3 0.6 100 0 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb - 0.6 0.6 0.6 - 1.3 400 - - - 0.9 300 300 1000 400 - - - 50 - kHz s s ns s ns ns ns pF s s s ns s
2. RES may be LOW before VDD1 goes HIGH. 3. If tW(RES) is longer than 3 ns (typical) a reset may be generated. 4. All timing values are valid within the operating supply voltage and ambient temperature ranges and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 5. The rise and fall times specified here refer to the driver device (i.e. not PCF8548) and are part of the general fast I2C-bus specification. When PCF8548 asserts an acknowledge on SDA, the minimum fall time is 10 ns. Cb = capacitive load per bus line. 6. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width 1999 Aug 16
24
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
17 RESET
PCF8548
handbook, full pagewidth
VDD t W(RES) RES t W(RES) VDD t VHRL RES t W(RES) t W(RES)
MGS404
Fig.17 Reset timing.
1999 Aug 16
25
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
18 APPLICATION INFORMATION Table 7 STEP B7 1 2 3 4 0 0 0 1 0 0 1 0 1 B6 B5 B4 1 0 0 B3 1 0 0 B2 0 0 0 B1 0 0 0 B0 0 0 1 I2C-bus start Programming example for PCF8548 BITS DISPLAY
PCF8548
OPERATION
slave address for write control byte with cleared Co bit and D/C set to logic 0 function set; PD = 0; V = 0; select extended instruction set (H = 1 mode) set bias system 2; this is the recommended bias system for a multiplex rate 1 : 65 set VOP; VOP is set to a +106 x b [V]; it should be noted that the required voltage is dependent on the liquid function set; PD = 0; V = 0; select normal instruction set (H = 0 mode) display control; set normal mode (D = 1; E = 0) restart; to write into the display RAM the D/C must be set to logic 1; therefore a control byte is needed
5
0
0
0
1
0
0
1
0
6
1
1
1
0
1
0
1
0
7
0
0
1
0
0
0
0
0
8 9
0
0
0
0
1
1
0
0
I2C-bus start
10 11 12
0 0 1
1 1 1
1 0 1
1 0 1
1 0 1
0 0 0
0 0 0
0 0 0
slave address for write control byte with cleared Co bit and D/C set to logic 1 data write; Y and X are initialized to 0 by default, so they are not set here
MGS405
13
1
0
1
0
0
0
0
0
data write
MGS406
1999 Aug 16
26
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
BITS STEP B7 14 1 B6 1 B5 1 B4 0 B3 0 B2 0 B1 0 B0 0 data write DISPLAY OPERATION
MGS407
15
0
0
0
0
0
0
0
0
data write
MGS408
16
1
1
1
1
1
0
0
0
data write
MGS409
17
0
0
1
0
0
0
0
0
data write
MGS410
18
1
1
1
1
1
0
0
0
data write
MGS411
19 20 21 22 0 1 0 1 0 0 1 0 0
I2C-bus start 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1
restart slave address for write control byte with set Co bit and D/C set to logic 0 display control; set inverse video mode (D = 1; E = 1)
MGS412
23 24
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
control byte with set Co bit and D/C set to logic 0 set X address of RAM; set address to `0000000'
MGS413
1999 Aug 16
27
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
BITS STEP B7 25 26 1 0 B6 1 0 B5 0 0 B4 0 0 B3 0 0 B2 0 0 B1 0 0 B0 0 0 control byte with set Co bit and D/C set to logic 1 data write DISPLAY OPERATION
MGS414
27 28
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
control byte with cleared Co bit and D/C set to logic 0 set X address of RAM; set address to `0000000'
MGS415
29 30 31 32 0 1 1 1 1 1 1 0 1
I2C-bus start 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0
restart slave address for write control byte with set Co bit and D/C set to logic 1 write data
MGS416
33
1
0
0
0
0
0
0
0
control byte with set Co bit and D/C set to logic 0
handbook, halfpage
VDD1
SCL
SCL VDD1 MICROCONTROLLER SDA
MGS417
PCF8548
SDAIN SDAOUT
Fig.18 Connecting the I2C-bus interface.
1999 Aug 16
28
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
DISPLAY 102 x 65
32
102
33
VDD2,3 VDD1
PCF8548
VSS1 VSS2 CVDD VSS
3 CVLCD
MGS418
I/O
VDD
The number of I/Os depends on the application.
Fig.19 Internal charge pump is used and a single supply voltage.
handbook, full pagewidth
DISPLAY 102 x 65
32
102
VLCDSENSE VLCDOUT VLCDIN
33
VDD2,3 VDD1
PCF8548
VSS1 VSS2 CVDD1 CVDD2 VSS
3 VDD1 I/O VDD2
CVLCD
The number of I/Os depends on the application.
Fig.20 Internal charge pump is used and two separate supply voltages.
1999 Aug 16
29
VLCDSENSE VLCDOUT VLCDIN
MGS419
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
DISPLAY 102 x 65
32
102
33
VDD2,3 VDD1
PCF8548
VSS1 VSS2 CVDD VSS
3
I/O
VDD
VLCDSENSE VLCDOUT VLCDIN VLCD
MGS420
The number of I/Os depends on the application.
Fig.21 External high voltage generation is used.
The pinning of the PCF8548 is optimized for single plane wiring e.g. for chip-on-glass display modules, or for TCP. Display size: 65 x 102 pixels. The required minimum value for the external capacitors in an application with the PCF8548 are: CVDD, CVDD1, CVDD2 and CVLCD = 1.0 F (min.). Higher capacitor values are recommended for ripple reduction. To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application, it is strongly recommended to implement on the glass (ITO) a series input resistance in the reset line (The recommended minimum value is 8 k). 19 CHIP INFORMATION The PCF8548 is manufactured in n-well CMOS technology. The substrate is at VSS potential. 20 PAD INFORMATION PAD Minimum bump pitch Pad size, alumin Bumps Wafer thickness without bumps 70 62 x 100 50 (6) x 90 (6) x 17.5 (5) U/2 = 381; U/9 = 525 VALUE m m m m UNIT
1999 Aug 16
30
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Table 8 Bonding pad location All x and y coordinates are referenced to the centre of the chip (dimension in m; see Fig.22). SYMBOL RES SDAOUT SDAIN SDAIN SCL SCL T2 SA0 T7 T6 T5 T4 T3 T1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 dummy pad VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSENSE VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN 1999 Aug 16 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 x +1160 +840 +600 +520 +200 +120 -200 -410 -620 -830 -1040 -1250 -1460 -1670 -1750 -1830 -1910 -1990 -2070 -2150 -2310 -2390 -2470 -2550 -2630 -2710 -2790 -2950 -3030 -3110 -3190 -3270 -3350 -3430 -3510 -3590 -3670 -3750 -3830 -3910 y +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 31 SYMBOL R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 dummy pad dummy pad R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 C0 C1 C2 C3 C4 PAD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 x -4235 -4305 -4375 -4445 -4515 -4585 -4655 -4725 -4795 -4865 -4935 -5005 -5075 -5145 -5355 -5320 -5040 -4970 -4900 -4830 -4760 -4690 -4620 -4550 -4480 -4410 -4340 -4270 -4200 -4130 -4060 -3990 -3920 -3850 -3780 -3570 -3500 -3430 -3360 -3290
PCF8548
y +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
SYMBOL C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 PAD 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 x -3220 -3150 -3080 -3010 -2940 -2870 -2800 -2730 -2660 -2590 -2520 -2450 -2380 -2310 -2240 -2170 -2100 -2030 -1960 -1890 -1750 -1680 -1610 -1540 -1470 -1400 -1330 -1260 -1190 -1120 -1050 -980 -910 -840 -770 -700 -630 -560 -490 -420 -350 -280 y -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 SYMBOL C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 PAD 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 x -210 -140 -70 +0 +140 +210 +280 +350 +420 +490 +560 +630 +700 +770 +840 +910 +980 +1050 +1120 +1190 +1260 +1330 +1400 +1470 +1540 +1610 +1680 +1750 +1820 +1890 +2030 +2100 +2170 +2240 +2310 +2380 +2450 +2520 +2590 +2660 +2730 +2800
PCF8548
y -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4
1999 Aug 16
32
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
SYMBOL C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 R50 R49 R48 R47 R46 R45 R44 R43 R42 R41 R40 R39 R38 R37 R36 R35 R34 R33 dummy pad dummy pad R51 R52 R53 R54 R55 R56 R57 R58 R59 PAD 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 x +2870 +2940 +3010 +3080 +3150 +3220 +3290 +3360 +3430 +3500 +3570 +3640 +3710 +3850 +3920 +3990 +4060 +4130 +4200 +4270 +4340 +4410 +4480 +4550 +4620 +4690 +4760 +4830 +4900 +4970 +5040 +5320 +5355 +5145 +5075 +5005 +4935 +4865 +4795 +4725 +4655 +4585 y -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 -899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 SYMBOL R60 R61 R62 R63 R64 T12 T11 T10 T9 OSC T8 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Table 9 PAD 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 x +4515 +4445 +4375 +4305 +4235 +3880 +3720 +3560 +3400 +3160 +2680 +2600 +2520 +2440 +2360 +2280 +2200 +2120 +2040 +1960 +1880 +1800 +1720 +1640 +1560 +1480 +1400
PCF8548
y +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4
Alignment marks x y -899.4 -899.4 +899.4 +899.4 MARKS mark 1 mark 2 mark 3 mark 4
+5214 -5214 +4099 -4099
The alignment marks are circular with a diameter of 100 m.
1999 Aug 16
33
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Aug 16
VLCDSENSE VLCDOUT VLCDIN dummy dummy row 19 VSS2 VSS1 row 32 T1 T3 T4 T5 T6 T7 SA0 T2 alignment mark
Philips Semiconductors
SDAOUT
SDAIN
RES
SCL
pad No.1
PC8548-1
y
alignment mark
alignment mark
0, 0
x
dummy
col 101 row 50
row 18 col 0
row 33
MGS421
dummy
row 0
alignment mark
row 51 dummy
VDD2
VDD3
VDD1
OSC
T9 T10 T11 T12
row 64
T8
handbook, full pagewidth
65 x 102 pixels matrix LCD driver
. . .
. . .
. . .
. . .
34
Maximum chip size: 2.12 mm x 10.99 mm.
. . .
. . .
. . .
. . .
. . .
. . .
Product specification
PCF8548
Fig.22 Bonding pad location.
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
R64 R63 . . . . . R52 R51
R50 R49 . . . . . R34 R33
TRS = 1
BRS = 1
COLUMNS
PC8548-1
R19 R20 . . . . . R31 R32
PC8548-1
MX = 1
C0 C1 . . .
PC8548-1
. . . C100 C101
MGS657
Fig.23 Pad layout for BRS, TRS and MX.
1999 Aug 16
35
COLUMNS R0 R1 . . . . . R17 R18
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
21 DEVICE PROTECTION DIAGRAM
PCF8548
handbook, full pagewidth
VDD1
VDD1
VSS1
VSS1 VDD2
T2
VSS1 VSS1 VSS2 VDD3 VSS1
VDD1 T3, T4
VSS1
VSS1 VSS2
VLCDIN T9 T10 T11 T12 VSS1 VSS1
VSS1
VSS1 VLCDIN VLCDOUT VLCDSENSE
VSS1
VSS1 VDD1 SA0 OSC RES T1 T5 to T7
COL 0-101/ ROW 0-64 VLCDIN 1 per block
VSS1
VSS1
MGS422
VSS1
T8
VSS1
VSS1
Fig.24 Device protection diagram.
1999 Aug 16
36
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
22 TRAY INFORMATION
x
PCF8548
handbook, full pagewidth
A
C
y
D
B F
E
MGS423
The dimensions are given in Table 10.
Fig.25 Tray details.
Table 10 Dimensions DIM. A B C
handbook, halfpage
DESCRIPTION pocket pitch, x direction pocket pitch, y direction pocket width, x direction pocket width, y direction tray width, x direction tray width, x direction number of pockets in x direction number of pockets in y direction
VALUE 13.77 mm 4.45 mm 11.09 mm 2.3 mm 50.8 mm 50.8 mm 3 10
D E F
PC8548-1
x y
MGS424
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
Fig.26 Tray alignment.
1999 Aug 16
37
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
23 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Application information Where application information is given, it is advisory and does not form part of the specification. 24 LIFE SUPPORT APPLICATIONS
PCF8548
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 25 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
26 BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1999 Aug 16
38
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
NOTES
PCF8548
1999 Aug 16
39
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/02/pp40
Date of release: 1999
Aug 16
Document order number:
9397 750 05023

▲Up To Search▲

Price & Availability of PCF8548U2

	To Download PCF8548U2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .